1. Field of the Invention
The present invention relates to an arithmetic circuit for adaptive equalizer of LMS (Least Mean Square) algorithm, and more specifically to an arithmetic circuit for adaptive equalizer of LMS algorithm, which reduces an amount of operations.
2. Description of Related Art
In data transmission systems, equalizers are used so as to remove intersymbol interferences thereof. Adaptive equalizers can eliminate intersymbol interferences in accordance with fluctuations of properties of data transmission systems in time.
An adaptive equalizer of LMS algorithm renews an adaptation coefficient according to following equations: EQU C.sup.i.sub.n+1 =C.sup.i.sub.n -.alpha.D.sup.i.sub.n E.sup.i.sub.n( 1)
C.sup.i.sub.n+1 : filter coefficient sequence at a sample time of n + 1 PA1 C.sup.i .sub.n : filter coefficient sequence at a sample time of n PA1 .alpha.: step coefficient PA1 D.sup.i.sub.n : data sequence at a sample time of n PA1 E.sup.i.sub.n : error sequence at a sample time of n PA1 a real operation part computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and computing a second product between an imaginary part signal of the data sequence and product of an imaginary part signal of the error sequence and a step coefficient, wherein either of the first and second products is negative, so as to obtain a real part of an adaptation coefficient from the first and second products; and PA1 an imaginary operation part computing a third product between the imaginary part signal of the data sequence and product of the real part signal of the error sequence and the step coefficient, and computing a fourth product between the real part signal of the data sequence and product of the imaginary part signal of the error sequence and the step coefficient, so as to obtain an imaginary part of an adaptation coefficient from the third and fourth products.
By expanding .alpha.D.sub.n.sup.i E.sub.n.sup.i of the equation (1) into a real part and an imaginary part, the following equations are obtained: EQU D.sup.i.sub.n =.alpha.+jb (2) EQU E.sup.i.sub.n =c-jd (3) EQU .alpha.D.sup.i.sub.n E.sup.i.sub.n =.alpha.(a+jb)(c-jd) =.alpha.(ac+bd)+j.alpha.(bc-ad) (4)
The filter coefficient sequence at a sample time of n+ 1 is a difference between the filter coefficient sequence at a sample time of n and .alpha.D.sup.i.sub.n E.sup.i.sub.n so that renewal of the adaptation coefficient is determined by the adaptation coefficient .alpha.D.sup.i.sub.n E.sup.i.sub.n.
Referring to FIG. 1, a conventional arithmetic circuit for adaptive equalizer will be explained. There is shown a block diagram of a conventional arithmetic circuit for adaptive equalizer in FIG. 1. The arithmetic circuit comprises a multiplier 1 computing a product of a real part signal 103 (c of the above mentioned equations) of the error sequence E.sup.i.sub.n (c-jd of the above mentioned equations) and the step coefficient 105 (.alpha.of the above mentioned equations), and a multiplier 2 computing a product of an imaginary part signal 104 (d of the above mentioned equations) of the error sequence E.sup.i.sub.n (c-jd) and the step coefficient 105 (.alpha.). The arithmetic circuit also comprises a multiplier 4 computing a product of a real part signal 101 (.alpha. of the above mentioned equations) of the data sequence D.sup.i.sub.n (a+jb of the above mentioned equations) and a real part signal 106 (.alpha. of the above mentioned equations) of the real part signal 103 (c) of the error sequence E.sup..sub.n (c-jd) and the step coefficient 105 (.alpha.). The arithmetic circuit further comprises a multiplier 5 computing a product of an imaginary part signal 102 (b of the above mentioned equations) of the data sequence D.sup.i.sub.n (a+jb) and an imaginary signal 107 (.alpha.d of the above mentioned equations). In addition, the arithmetic circuit comprises a multiplier 6 computing a product of the imaginary part signal 102 (b) and the real part signal 106 (.alpha.c) and a multiplier 7 computing a product of the real part signal 101 (a) of the data sequence D.sup.i.sub.n (a+jb) and the imaginary signal 107 (.alpha.d).
The multipliers 4, 5, 6 and 7 respectively send a real signal 108 (.alpha.ac) of the above mentioned equations), real signal 114 (.alpha.bd) of the above mentioned equations), imag signal 110 (.alpha.bc of the above mentioned equations) and imag signal 111 (.alpha.ad of the above mentioned equations) to rounding processors 10, 11, 12 and 13. The rounding processors 10, 11, 12 and 13 round the real signals 108 (.alpha.ac) and 114 (.alpha.bd), and imag signals 110 (.alpha.bc) and 111 (.alpha.ad) so as to send rounded signals 115 and 116 to an adder 14 and rounded signals 117 and 118 to a subtracter 9. The adder 14 adds the rounded signals 115 and 116 so as to obtain a real part 112 of an adaptation coefficient. The subtracter 9 subtracts the rounded signal 118 from the rounded signal 117 so as to obtain an imaginary part 113 of an adaptation coefficient.
When the filter of the adaptive equalizer is implemented by a fixed-point DSP (Digital Signal Processor), the product is always truncated regardless of positive or negative due to fixed-point arithmetic. By this, negative errors are produced in the multipliers 4 to 7. If the arithmetic is carried out with the above errors, the errors are accumulated to the filter coefficient so that a theoretical result cannot be obtained. In order to prevent this problem, the outputs of the multipliers of the arithmetic circuit shown in FIG. 1 are rounded so as to reduce multiplication errors produced in the multipliers.
However, operations for the rounding process are one third of the whole operations of the arithmetic circuit so that high speed operations are difficult.